Existing I/O Channel Subsystems (IOSS) only provide direct support for I/O instructions issued by a host central processor which initiate execution of I/O channel programs located in the host main memory, and for I/O interruptions resulting from the execution of such I/O channel programs. Other I/O related functions must be executed by a central processor (CPU), which must issue an I/O instruction to the IOSS to start execution of a channel program that will use the results of such CPU executed I/O related functions. The latter processing is an interface between the IOSS and such CPU executed I/O related functions, which is indirect.
Dedicated I/O adapter functions connected with the IOSS have been performed in the prior art using unique hardware entities external to the IOSS, such as channel-to-channel hardware coupling devices, and special hardware semiconductor chips for performing special functions such as compression/decompression, cryptography, LAN network conversion operations, etc.
The IOSS operates as a protected and privileged part of a computer system. The IOSS does not execute ordinary CPU instructions, and CPUs have only limited access to the IOSS through a small set of privileged CPU-I/O instructions. Its protected state does not allow the IOSS to be accessed by any application programs executing in problem state, and general access to the IOSS is not provided even to the privileged OS program. The CPU's problem state and privileged instructions are all located in the same real memory with the I/O channel programs. That is, I/O channel programs are not located in the IOSS. And the IOSS cannot execute non-privileged CPU instructions.
The present invention finds use in a data processing system such as one produced by International Business Machines Corp. and referred to as an ES/9000. This data processing system is configured to comply with an architecture defined in "IBM System ESA/390 Principles of Operation", SA22-7201.
A portion of FIG. 1 will be referred to for describing the existing flow of I/O functions and operations through the data processing system, as may be found in the prior art, as follows:
The data processing system includes a host computer comprised of one or more central processing units (CPUs) 9 and a host memory 6. Host memory 6 is comprised of a main store 7, addressable by program instructions such as contained in the system control program 11 and user programs and a system store 8. The system store stores various control data and is only available to various hardware components and microcode such as the CPU microcode 12. This system store is not available to program instructions.
The data processing system also includes an input/output subsystem (IOSS) 10 which provides the communication between the CPUs 9 and a plurality of I/O devices 5. The IOSS 10 includes a plurality of channels 15 that provide the physical connection to the I/O devices 5, and a set of processes within IOSS MAIN 14. These processes include those that accept requests for I/O functions from the CPUs 9, those that execute these I/O functions, and those that select a channel 15 and dispatch I/O operations with the I/O devices 5. The I/O operations consist of sequences that perform read, write and control operations with the I/O devices 5. A read operation causes data stored on a device 5 such as a disk drive to be transferred to main store 7 and make it available for use by program instructions. A write operation causes data in main store to be transferred to a device 5 such as a printer or storage device. A control operation causes special functions to occur at the I/O device 5 such as a rewind operation for a tape drive. These processes also include those that accept ending status from the devices 5 and present the status to the CPU 9.
In accordance with the ESA/390 architecture, each I/O device is represented by a subchannel (SCH) 4. Each subchannel is assigned a unique number called a subchannel number and contains the information necessary to perform I/O functions and operations with the associated device. These subchannels are typically predefined by the customer according to the set of installed devices and their characteristics. An I/O instruction executed by the SCP 11 in a CPU 9 targets a SCH 4 using the subchannel number. The CPU microcode 12 interprets the instruction. If the I/O instruction is asynchronous, the CPU microcode 12 sets up the SCH 4, queues it on a work queue and provides initiative for the IOSS 10 to look at the work queue; Signal Work--SIGW.
Subsequently, the IOSS 10 recognizes that work is pending on its work queue, dequeues the SCH 4 from the work queue using the Dequeue Work process 13 and executes the I/O function pending in the SCH using the IOSS MAIN process 14. This may include dispatching the I/O function on a channel 15 to a device 5 to execute a sequence of I/O operations also known as a channel program stored in main store 7. When a channel program completes and the device 5 presents ending status to the channel 15, the channel provides initiative for the IOSS MAIN 14 to update the state of the subchannel and make it status pending. The SCH 4 is queued on the interruption queue using the Enqueue Interruption process 18 and an I/O interruption is signaled to the CPU 9; Signal Interruption--SIGI.
Subsequently, the I/O interruption is detected by the CPU microcode 12, accepted by the SCP 11 and the status is tested and cleared from the SCH 4.